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YMU765 ma-5 mobile audio 5 yamaha corporation YMU765 catalog catalog no : lsi-4mu765a2 2003.7 outline YMU765 is a synthesizer lsi for mobile phones that realize advanced game sounds of java application program etc. this lsi has a built-in speaker amplifier, and thus, is an ideal device for outputting sounds that are used by mobile phones in addition to game sounds and ringing melodies that are replayed by a synthesizer. the synthesizer section adopts the ?stereophonic hybrid synthesizer system? which is given advantages of both fm synthesizers and wave table synthesizers to allow simultaneous generation of up to 32 fm voices and 32 wave table voices. furthermore, the stream playback function, the vo ice synthesis function by hv (humanoid voice) synthesizer (*), and the time-variant low pass filter function by al (analog lite) synthesizer have also on board. since fm synthesizer is able to present countless voices by specifying parameters with only several tens of bytes, memory capacity and communication band can be saved, and thus, the device exhibits the features in operating environment of mobile phones such as allowing distribution of arbitrary melodies with voices. on the other hand, wave table synthesizer can pronounce the voice built in rom and arbitrary adpcm/pcm voices from sequencer by the download of the melody with voices etc.. YMU765 has a built-in hardware sequencer that helps to rea lize a complex play without heavily loading the host cpu. in addition, it is possible to create more highly efficient a pplications by the voice synthesis function (*) and the function of time-variant low pass filter. moreover, the device also has a built-in circuit for controlling vibrators and leds synchronizing with play of music. (*) hv synthesizer function only responds to japanese and korean language at present. features built-in the hybrid synthesizer, and possible to generate 64 tones simultaneously as maximum. voice synthesis voice function by hv (h umanoid voice) synthesizer is on board. (*) hv synthesizer function only responds to japanese and korean language at present. the time fluctuation low pass filter function by al (analog lite) synthesizer is on board. stream replay with adpcm / pcm is possible. has built-in default voices for fm and wave table synthe sizers in the rom, and the voices can be downloaded to ram. equipped with speaker amplifier and equalizer circuit. equipped with a stereophonic output terminal for headphone. equipped with vibration control circuit, and led lighting control circuit. has built-in pll and inputting of master clock up to 20 mh z is possible and compiles with the tcxo (temperature compensated crystal oscillator). contains a 16-bit stereophonic d/a converter. has power down mode. power supply for core 2.65v 3.30v power supply for i/o 1.65v vdd power supply for speaker amplifier vdd 4.50v 32-pin qfn plastic package
YMU765 2 pin configuration 16 15 14 13 12 11 10 spvss spvdd eq3 eq2 eq1 hpout-r hpout-l/mono vref vss vdd pllc n.c /rst /irq led clki spout1 spout2 mtr d7 d6 d5 d4 d3 d2 26 27 28 29 30 31 32 d1 d0 /wr /cs a0 /rd iovdd 25 24 23 22 21 20 19 18 17 123456789 <32pin qfn top view>
YMU765 3 pin functions no. pin name i/o power supply function 1 clki ish vdd clock input (1.5 mhz 20 mhz) correspond with tcxo. 2 led o iovdd external led control 3 /irq o iovdd interrupt output 4 /rst ish iovdd hardware reset input 5 n.c no connection (be sure to use without connection.) 6 pllc a vdd connection of capacitor for built-in pll connect a series connection of 1000 pf capacitor and 3.3 k ? resistor between this pin and vss(*). (*)directly connect vss used here and vss of 8 th pin. 7 vdd power supply (2.65 3.30v) connect 0.1 f and 4.7 f capacitors between this pin and vss. 8 vss ground 9 vref a vdd analog reference voltage: connect 0.1 f capacitor between this pin and vss. 10 hpout-l / mono a vdd headphone output lch ( can be used as mono output ) 11 hpout-r a vdd headphone output rch 12 eq1 a vdd equalizer pin 1 13 eq2 a vdd equalizer pin 2 14 eq3 a vdd equalizer pin 3 15 spvdd speaker amplifier analog power supply (vdd 4.50v) connect 0.1 f and 4.7 f capacitors between this pin and spvss. 16 spvss speaker amplifier analog ground 17 spout1 a spvdd speaker connection pin 1 18 spout2 a spvdd speaker connection pin 2 19 mtr o iovdd external motor control pin 20 d7 i/o iovdd cpu i/f data bus 7 21 d6 i/o iovdd cpu i/f data bus 6 22 d5 i/o iovdd cpu i/f data bus 5 23 d4 i/o iovdd cpu i/f data bus 4 24 d3 i/o iovdd cpu i/f data bus 3 25 d2 i/o iovdd cpu i/f data bus 2 26 d1 i/o iovdd cpu i/f data bus 1 27 d0 i/o iovdd cpu i/f data bus 0 28 /wr i iovdd cpu i/f write enable 29 /cs i iovdd cpu i/f chip select 30 a0 i iovdd cpu i/f address signal 31 /rd i iovdd cpu i/f read enable 32 iovdd pin power supply (1.65 vdd) a : analog pin ish : schmitt input
YMU765 4 block diagram eq vol led control vibrator control timer hpout-l / mono hpout-r 16-bit dac lch rch clki vdd vss pllc cpu i/f timing generator pll /irq led mtr /rst a0 /wr /rd d0 - d7 /cs eq1 spvdd spvss eq2 eq3 vref + - vref sp vol spout1 spout2 analog power supply dedicated to speaker amp mono rch lch iovdd fifo 512byte fifo 64byte instantaneous write path delayed write path instantaneous read path software irq, stream playback irq hybrid synthesizer vref control register & sram / rom interface register intermediate register hp voll hp volr sequencer
YMU765 5 outline of blocks this section outlines f unctions of blocks contained in th is device and flow of signals. cpu interface fifo fifo sequencer synthesizer dac eq amp speaker amp headphone output instantaneous write path delayed write path instantaneous read path clock generator clock input led control vibrator control interface register intermediate register control register rom/ ram cpu interface cpu interface is an 8-bit parallel type. it assumes that a total of 13 pins of 4 control signals (/wr, /rd, /cs, a0 pin), 8 data bus (d0 to d7), and 1 interrupt pin (/irq) are connected to the external cpu. this block co ntrols the writing and reading of data by the input polarity of control signal. interface register this register is able to access directly from the external cpu. there are 2 bytes spaces. the latter intermediate register can be accessed through the interface register. intermediate register this register is accessed through the interface register. the ?control register? and rom/sram, which describes below, can be accessed through this register. this register is called the ?intermediate register? since this exists in the middle of the interface register and the control register. in the intermediate register, there are some registers to control various functions. control register, rom/sram the control register and rom/sram are accessed from ?instant aneous write register?, ?delayed write register?, and ?instantaneous read register? in the intermediate register. in the control register, there is a register to control the following synthesizer mainly. the voice parameter for fm (gm 128 voices + drum 40 voices) and wave data for wt are stored in rom. sram is used at the download of arbitrary fm voice parameter and wave data for wt. moreover, it is used as storing buffer at the stream playback of pcm/adpcm. fifo this is an abbreviation of ?first in first out? means the memory which data is read in order of written. there are 2 paths to write into fi fo in the intermediate register. the ?instantaneous write path? is for accessing the control register and rom/sram immediately, also ?delayed write path? is for accessing the control register after managing time through the sequencer. fifo size of instantaneous path is 64-byte, and its size of delayed path is 512-byte.
YMU765 6 sequencer this is for interpreting the contents of data which was written into the delayed write path. generally, ?music data? is written into the delayed write path . it interprets the contents of music data and controls the synthesizer after sequencer, and then plays the music. hybrid synthesizer this device contains a built-in polyphonic synthesizer that adopts a stereophonic hybrid system that generates up to 64 tones. fm synthesizer, wt (wave table) synthesizer, stream playback, hv (humanoid voice) synthesizer (*), and al (analog lite) synthesizer are available. (*) hv synth esizer function only responds to japanese and korean language at present. led, vibrator control it is possible to synchronize an led and vibrator with a play, and to control. a synchronous control to a play is also possible. clock generating block this device supports a clock input ranging from 1.5 mhz to 20 mhz. (stop = 0 hz is possible at power down.) it is a block to generate a clock which is needed inside of lsi in the pll. dac it converts digital signals from a synthesizer and a digital audio section into analog signals. the length of a data is 16bits. headphone output this is an amplifier of stereophonic output for headphone. the monaural output is also possible. eq amplifier the change of filter characteristic and gain is possi ble by adjusting the resistors and external parts. speaker amplifier a speaker amplifier, which has maximum output power of 580 mw at spvdd=3.6v, is integrated this device. there is a volume to adjust output le vel in the first part of amplifier.
YMU765 7 electrical characteristics absolute maximum rating item symbol min. max. unit spvdd pin, power supply voltage (speaker amplifier section) spvdd -0.3 6.0 v vdd pin, power supply voltage vdd -0.3 4.2 v iovdd pin, power supply voltage iovdd -0.3 4.2 v spout1, spout2 pin, applied voltage v insp -0.3 spvdd+0.3 v analog input voltage v ina -0.3 vdd+0.3 v digital input voltage 1 (*1) v ind1 -0.3 iovdd+0.3 v digital input voltage 2 (*2) v ind2 -0.3 vdd+0.3 v permissible loss (*3) pd 1197 mw storage temperature t stg -50 125 c [condition] vss = spvss = 0v (*1) target pin: d0 d7, /cs, a0, /wr, /rd, /rst (*2) target pin: clki (*3) top= 25 c, and glass epoxy pcb (30mm 100mm 1.0mm) is installed. when operating above top= 25 c, permissible loss decreases 12 mw per 1 c. recommended operating conditions item symbol min. typ. max. unit spvdd operating voltage (speaker amplifier section) spvdd vdd 3.60 4.50 v vdd operating voltage vdd 2.65 3.00 3.30 v iovdd operating voltage iovdd 1.65 1.80 vdd v operating ambient temperature t op -20 25 85 c [condition] vss = spvss = 0v power consumption item conditions typ. max. unit power consumption of vdd+iovdd normal operation (*1) 40 ma at silent sound generated spvdd side 4 ma at the time of output 400mw / 8ohm load spvdd side 210 ma power down mode ta = +25c vdd+iovdd+spvdd (*2) 0.5 2 a power down mode ta = +85c vdd+iovdd+spvdd (*2) 10 a (*1) vdd=iovdd=3.00v , spvdd=3.60v, t op =25c (*2) vdd=iovdd=3. 30v, spvdd=4.50v /cs input pin is fixed to v ih =iovdd, the other input pins are v il =vss and v ih =(io)vdd.
YMU765 8 dc characteristics item symbol condition min. typ. max. unit input voltage ?h? level 1 v ih (*1) 0.65 iovdd v input voltage ?l? level 1 v il (*1) 0.35 iovdd v input voltage ?h? level 2 v ih (*2) 0.75 iovdd v input voltage ?l? level 2 v il (*2) 0.25 iovdd v input voltage ?h? level 3 v ih (*3) 0.70 vdd v input voltage ?l? level 3 v il (*3) 0.30 vdd v output voltage ?h? level v oh (*4) i oh = (*5) 0.80 iovdd v output voltage ?l? level v ol (*4) i ol = (*5) 0.20 iovdd v schmitt width 1 vsh1 /rst pin 0.10iovdd v schmitt width 2 vsh2 clki pin 0.10vdd v input leakage current il -1 1 a input capacity ci 10 pf [condition] t op =-20 85c, vdd=2.65 3.30v, iovdd=1.65 vdd[v], capacitor load=50 pf (*1) target pin: d0 d7, /cs, a0, /wr, /rd (*2) target pin: /rst (*3) target pin: clki (in the case of cmos mode) (*4) target pin: d0 d7, /irq, led, mtr (*5) /irq, d0 ~ d7, are i oh = ?1 ma, i ol = +1 ma led, mtr are i oh = ?4 ma, i ol = +4 ma however, when iovdd is less than 2.65v, d0 d7, /irq, led, and mtr become i oh =-0.2ma and i ol =+0.2ma.
YMU765 9 ac characteristics reset and clock timing /rst, clki (cmos mode), other input signals item symbol min. typ. max. unit /rst ?l? pulse width t rstw 100 s /rst (indefinite l) setup time t rsts 0 s vdd - iovdd rise time difference t vskw 0 3 ms clki frequency 1 / tfreq 1.5 20 mhz clki rise / fall time trckc / tfckc 30 ns clki high time th 15 ns clki low time tl 15 ns input signals other than clki rise / fall time tr / tf 20 ns [condition] t op =-20 85c, vdd=2.65 3.30v, iovdd=1.65 vdd[v], capacitor load=50 pf the input to clock can be stopped (=0hz) during reset period and power down state (dp0=1). however, the input level is to be h or l, and input of intermediate level is prohibited. when vdd and iovdd are used by respectively different power supply, make sure to rise from vdd first. the reset width is defined as the time from the moment iovdd has risen to 1.65v. /rst has to be settled at ?l? level at the time vdd has risen to 50%.
YMU765 10 clki (tcxo mode) item symbol min. typ. max. unit clki frequency 1 / tfreq 1.5 20 mhz clki rise / fall time trckt , tfckt 250 ns clki amplitude h vmax - vcenter 0.30 0.35 vdd v clki amplitude l vcenter - vmin 0.30 0.35 vdd v wait time to stable operation (*1) twait 2 ms feedback resistance rck 30 45 63 k ? [condition] t op =-20 85c, vdd=2.65 3.30v, capacitor load=50pf (*1) : the value at the ac coupling of tcxo parts and the clki pin by the capacity of 1000pf. ? the voltage level which duty of clki becomes 50% (high time = low time) is defined as vcenter. ? trckt and tfckt are defined by the change time between vcenter + 0.30[v] and vcenter - 0.30[v]. ? the timing observation level of tfreq is to be vcenter (duty=50%).
YMU765 11 cpu interface timing the ac characteristics of a cpu interface are measured on c ondition as follows. the input conditions at the time of measurement : v ih = 0.8iovdd, v il =0.2iovdd the measurement points : v ih = 0.65iovdd, v il =0.35iovdd v oh = 0.65iovdd, v ol =0.35iovdd cpu interface 1 (in the case of iovdd R 2.65v) (write cycle) item symbol min max. unit address setup time t ads 50 ns address hold time t adh 0 ns chip select setup time t css 50 ns chip select hold time t csh 0 ns write pulse width t ww 50 ns data setup time t wds 30 ns data hold time t wdh 0 ns [condition] t op =-20 85c, vdd=iovdd=2.65 3.30v, capacitor load=50 pf (read cycle) item symbol min max. unit access time from /rd pin t accrd 70 ns access time from /cs pin t acccs 70 ns access time from /a0 pin t acca0 70 ns data hold time from /rd pin t dhrd 0 ns data hold time from /cs pin t dhcs 0 ns data hold time from a0 pin t dha0 0 ns high-impedance transition time from /rd pin t dzrd 30 ns high-impedance transition time from /cs pin t dzcs 30 ns [condition] t op =-20 85c, vdd=iovdd=2.65 3.30v, capacitor load=50 pf i oh = -1.0ma, i ol = +1.0ma (d0 d7 pin)
YMU765 12 cpu interface 2 (in the case of iovdd < 2.65v) (write cycle) item symbol min max. unit address setup time t ads 50 ns address hold time t adh 0 ns chip select setup time t css 50 ns chip select hold time t csh 0 ns write pulse width t ww 50 ns data setup time t wds 50 ns data hold time t wdh 0 ns [condition] t op =-20 85c, vdd=2.65 3.30v, iovdd=1.65 less than 2.65v, capacitor load=30 pf (read cycle) item symbol min max. unit access time from /rd pin t accrd 80 ns access time from /cs pin t acccs 80 ns access time from /a0 pin t acca0 80 ns data hold time from /rd pin t dhrd 0 ns data hold time from /cs pin t dhcs 0 ns data hold time from a0 pin t dha0 0 ns high-impedance transition time from /rd pin t dzrd 50 ns high-impedance transition time from /cs pin t dzcs 50 ns [condition] t op =-20 85c, vdd=2.65 3.30v, iovdd=1.65 less than 2.65v, capacitor load=30 pf i oh = -0.2ma, i ol = +0.2ma (d0 d7 pin)
YMU765 13 write cycle note : t adh : the hold time of a0 pin, which is defined with respect to the point where the rise of /wr has reached 0.65*iovdd under the condition that both two specifications (t csh , t wdh ) are secured more than minimum value (=0ns). t csh : the hold time of /cs pin, which is defined with respect to the point where the rise of /wr has reached 0.65*iovdd under the condition that both two specifications (t adh , t wdh ) are secured more than minimum value (=0ns). t wdh : the hold time of d0 d7 pins, which is defined with respect to the point where the rise of /wr has reached 0.65*iovdd under the condition that both two specifications (t adh , t csh ) are secured more than minimum value (=0ns). t ads : the hold time of a0 pin, which is defined with respect to the point where /wr has become invalid (0.35*iovdd) under the condition that all of three specifications (t css , t ww , t wds ) are secured more than minimum value. t css : the hold time of /cs pin, which is defined with respect to the point where /wr has become invalid (0.35*iovdd) under the condition that all of three specifications (t ads , t ww , t wds ) are secured more than minimum value.
YMU765 14 read cycle note : t acca0 : the access time until d0 d7 are defined (0.65*iovdd or 0.35*iovdd) after a0 is defined (0.65*iovdd or 0.35*iovdd). considers that /rd and /cs are defined beforehand (*1). t acccs : the access time until d0 d7 are defined (0.65*iovdd or 0.35*iovdd) after /cs is defined (0.35*iovdd). considers that a0 and /rd are defined beforehand (*1). t accrd : the access time until d0 d7 are defined (0.65*iovdd or 0.35*iovdd) after /rd is defined (0.35*iovdd). considers that a0 and /cs are defined beforehand (*1). t dhrd : the time (hold time) until d0 d7 output valid data after /rd becomes enable (=0.35*iovdd) under the condition that a0 and /cs secure sufficient hold time (*2). t dhcs : the time (hold time) until d0 d7 output valid data after /cs becomes enable (=0.35*iovdd) under the condition that a0 and /rd secure sufficient hold time (*2). t dha0 : the time (hold time) until d0 d7 output valid data after a0 becomes enable (0.65*iovdd or 0.35*iovdd) under the condition that /rd and /cs secure sufficient hold time (*2). t dzrd : the time until d0 d7 become high impedance status after /rd becomes disable (=0.65*iovdd) under the condition that a0 and /cs secure sufficient hold time (*2). t dzcs : the time until d0 d7 become high impedance status after /cs becomes disable (=0.65*iovdd) under the condition that a0 and /rd secure sufficient hold time (*2).
YMU765 15 (*1) ? defined beforehand.? means, in the case of /cs : the status that /cs is defi ned (0.35*iovdd) before more than the time of t acccs with respect to the point where d0 d7 are defined (0.65*iovdd or 0.35*iovdd). in the case of /rd : the status that /rd is defi ned (0.35*iovdd) before more than the time of t accrd with respect to the point where d0 d7 are defined (0.65*iovdd or 0.35*iovdd). in the case of a0 : the status that a0 is defined (0.35*iovdd or 0.65*iovdd) before more than the time of t acca0 with respect to the point where d0 d7 are defined (0.65*iovdd or 0.35*iovdd). (*2) ? sufficient hold time? means, at t dhrd measurement: the status that the enable time of a0 and /cs pins input are secured more than 0ns with respect to the point where d0 d7 can not hold valid data. at t dhcs measurement: the status that the enable time of a0 and /rd pins input are secured more than 0ns with respect to the point where d0 d7 can not hold valid data. at t dha0 measurement: the status that the enable time of /cs and /rd pins input are secured more than 0ns with respect to the point where d0 d7 can not hold valid data. (example: at t dhrd measurement)
YMU765 16 analog characteristics conditions of t op =25c, vdd=3.00v, iovdd=1.80v, and spvdd=3.60v apply to all items. sp amplifier item min. typical max. unit gain setting (fixed) 2 times min. load resistance (rl) 8 ? max. output voltage amplitude (rl=8 ? ) 6.0 vp-p max. output power (rl=8 ? , thd+n 1.0%) 580 mw thd + n (rl=8 ? , f=1 khz, output = 400mw) 0.025 % noise at no signal (a-filter: weighting filter) -90 dbv psrr (f=1 khz) 90 db amplitude center potential (vsel2, vsel1 =0, 0) 0.6vdd v (vsel2, vsel1 =0, 1) 0.5vdd v (vsel2, vsel1 =1, 0) 0.67vdd v differential output voltage 10 50 mv max. load capacity connectable to spout1 and spout2 pin (*) 1000 pf (*) : the maximum of 1000pf can be connected to spout1 pin, and the maximum of 1000pf can be connected to spout2 pin. eq amplifier item min. typical max. unit gain settable range 30 db max. output voltage amplitude 2.7 vp-p thd + n (f=1 khz) 0.05 % noise at no signal (a-filter) -90 dbv input impedance 10 m ? feedback resistance between eq2 and eq3 20 k ? sp volume item min. typical max. unit volume setting range -30 0 db volume step width 1 db thd + n (f=1 khz) 0.05 % eq volume item min. typical max. unit volume setting range -30 0 db volume step width 1 db noise at no signal (a-filter) -90 dbv max. output current 120 a max. output voltage amplitude 1.5 vp-p output impedance 300 600 ?
YMU765 17 hp volume item min. typical max. unit volume setting range -30 0 db volume step width 1 db noise at no signal (a-filter) -90 dbv max. output current 120 a max. output voltage amplitude 1.5 vp-p output impedance 300 600 ? vref item min. typical max. unit vref voltage 0.5vdd v dac item min. typical max. unit resolution 16 bit full scale output voltage 1.5 vp-p thd+n (f= 1 khz) 0.5 % noise at no signal (a-filter) -85 -80 dbv frequency response (f=50hz to 20 khz) -3.0 (*) +0.5 db (*): reduction of response in high frequency range caused by aperture effect
YMU765 18 external dimensions of package
YMU765 agency all rights reserved address inquiries to: semiconductor sales & marketing department head office 203, matsunokijima, toyooka-mura iwata-gun, shizuoka-ken, 438-0192, japan tel. +81-539-62-4918 fax. +81-539-62-5054 tokyo office 2-17-11, takanawa, minato-ku, tokyo, 108-8568, japan tel. +81-3-5488-5431 fax. +81-3-5488-5088 osaka office 3-12-12, minami senba, chuo-ku, osaka city, osaka, 542-0081, japan tel. +81-6-6252-6221 fax. +81-6-6252-6229 printed in japan 2003 the specifications of this product are subject to improvement changes without prior notice. notice

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